1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits and semiconductor devices, and, more particularly, to electrically programmable fuses (e-fuses) and methods of manufacturing e-fuses in the context of the gate last (replacement gate) approach.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer.
A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Particularly for transistor devices with very short channel lengths, for example, of some 10 nm, gate structures with high-k dielectric gate insulating layers and one or more metal layers functioning as a gate electrode have been provided that show improved operational characteristics as compared to conventional silicon dioxide/polysilicon gates. The high-k insulation layers may include or consist of tantalum oxide, hafnium oxide, titanium oxide or hafnium silicates, for example. Furthermore, in the high-k/metal gate (HKMG) technology, a thin “work function metal” layer is typically inserted between the high-k dielectric and the gate material placed above the high-k dielectric. The threshold voltage can thus be adjusted by varying the thickness of the metal layer. The gate metal layer may comprise, for example, tantalum (Ta), tungsten (W), titanium nitride (TiN) or tantalum nitride (TaN). On the other hand, the work function metal layer may comprise metals such as aluminum and lanthanum. Work function metals may also be included in the gate metal layer.
There are basically two well-known processing methods for forming a planar or 3D transistor with a HKMG structure: the so-called “gate last” or “replacement gate” technique and the so-called “gate first” technique. In the replacement gate technique, a so-called “dummy” or sacrificial gate structure is initially formed and remains in place as many process operations are performed to form the device, for example, the formation of doped source/drain regions, performing an anneal process to repair damage to the substrate caused by the ion implantation processes and to activate the implanted dopant materials. At some point in the process flow, the sacrificial gate structure is removed to define a gate cavity where the final HKMG gate structure for the device is formed. Using the “gate first” technique, on the other hand, involves forming a stack of layers of material across the substrate, wherein the stack of materials includes a high-k gate insulation layer, one or more metal layers, a layer of polysilicon and a protective cap layer, for example, silicon nitride. One or more etching processes are performed to pattern the stack of materials to thereby define the basic gate structures for the transistor devices.
Reducing the typical dimensions of integrated circuits also leads to an increased probability of failure of single chip components, which in turn results in a decrease of product yield. Typically, damage of a single component, such as a single metal link, a transistor or a resistor, causes the entire integrated circuit to be unusable. This is obviously in contrast with the semiconductor industry endeavor of achieving ever increasing product quality, reliability and throughput.
In order to improve the product yield, a technique has been developed of “trimming” or electrically excluding circuit blocks which are no longer operable. This technique, particularly used during manufacturing of memory arrays, relies on redundant circuit blocks which can be incorporated into the main integrated circuit and activated once a defective circuit portion has been detected. On the other hand, the defective circuit block may be trimmed or electrically removed by blowing a fuse or a group of fuses which can electrically disconnect the defective block from the main circuit when in the open configuration. Reprogramming of an integrated circuit is thus rendered possible in a dynamic manner, even after the chip has been manufactured.
One of the most successfully used types of fuses used for enabling dynamic chip reprogramming is the so-called electrically programmable fuse (e-fuse). The cross-section of a typical e-fuse 100 formed during a manufacturing flow according to the HKMG gate first technology is shown in FIG. 1.
E-fuse 100 is formed on an isolation region 112 of a substrate (not shown). The substrate may be any appropriate carrier for a semiconductor integrated device. The isolation region 112 may, for example, have been formed by means of shallow trench isolation (STI).
E-fuse 100 includes a metal layer 124 formed above the surface of the isolation region 112. The material or material mixture constituting the layer 124 are typically the same as the material or material mixture making up the gate metal layer in the HKMG technology. Although not shown in the figure, a high-k dielectric layer may be interposed between the metal layer 124 and the surface of the isolation region 112.
A semiconductor layer 144 is then formed on the metal layer 124. The semiconductor material forming the layer 144 is preferably the same material used for forming the gate material layer on the gate metal layer. Thus, the semiconductor layer 144 is usually comprised of polysilicon. A metal silicide layer 164, typically nickel silicide, is finally formed on the surface of the semiconductor layer 144. The metal silicide layer 164 is conveniently formed during the same silicidation process used for forming electrical contacts to the electrodes (gate, source and drain) of a FET.
The metal silicide layer 164 includes a first electrode 164a and a second electrode 164c arranged at opposite ends of the layer 164. The first electrode 164a and the second electrode 164c could, for example, be the anode and the cathode of the e-fuse 100. Contact terminals 174a and 174b are then formed so as to provide an electrical connection to the first electrode 164a and the second electrode 164c, respectively. The contact terminals 174a and 174b are typically comprised of a metal with a high electrical conductivity.
When the e-fuse 100 is un-programmed, the metal silicide layer 164 is continuous and provides an electrical connection between the first electrode 164a and the second electrode 164b, thus presenting a low electrical resistance between the terminals 174a and 174b. The e-fuse 100 may then be programmed by applying a predetermined electrical bias between terminals 174a and 174b, thereby inducing a current to flow across the e-fuse 100. Since the resistivity of the semiconductor layer 144 is much greater than that of the silicide layer 164, almost all current flows through the latter layer. If the current intensity exceeds a predetermined threshold, electromigration occurs in the silicide layer 164, resulting in transport of the metal silicide material constituting the layer 164 towards the anode. After a sufficient amount of material has been transferred, one of the two electrodes 164a and 164c representing the anode, the e-fuse 100 switches to the programmed state when a gap is formed in the metal silicide layer 164, thereby resulting in an open circuit between the two terminals 174a and 174b. The electrical resistance of the programmed e-fuse 100 thus rises by several orders of magnitude with respect to the resistance in the un-programmed state.
However, the configuration shown in FIG. 1 is not suitable in the context of the gate last (replacement gate) technology wherein silicon has to be protected from silicidation in order to remove all of the amorphous or polysilicon in order to replace it with a metal gate. Thus, conventional e-fuses with silicided (poly) silicon cannot be used within the replacement gate process. On the other hand, e-fuses realized in back end-of-line (Beol) stacks suffer from the need for relatively high currents for blowing the fuses.
In view of the situation described above, the present disclosure provides techniques that allow for the formation of semiconductor devices comprising reliably operating e-fuses in the context of HG/MG gate last processes and semiconductor devices operating e-fuses.